Abha Dargar* and Viranjay M. Srivastava Pages 319 - 325 ( 7 )
Aims: The semiconductor technology has a great impact on consistent growth in the Very-Large- Scale Integrated (VLSI) devices. The transistor size has been scaled down from micron to submicron and towards the nanometer regime in the past 30 years due to technological advancements. The most reliable solid-state device is Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) but this rapid decrease in the device dimensions with the advent of Moore's law follows several problems, such as Short Channel Effects (SCE's) and Hot Carrier Effects. The channel becomes too small at short channel effects that necessitate the analysis of the optimum device designs, in particular in the operating conditions. The charge-sheet model that can quickly analyze a long-channel device, currently in the subthreshold to saturation regime without any discontinuity, turns out to be inappropriate at reduced channel size.
Objectives: At the nano-scaling of the device, since the accumulation layer thickness is comparable to the device, the assumption of the channel as a thin sheet of charge vanishes. Though the depletion layers or zone are the regions of the absentia of charges mostly, the existence affects the device behavior and the channel thickness. Therefore, channel thickness modeling becomes essential at various bias conditions to define the specifics of device operation and the channel dependence of the structural parameters. In this work, the objective is to develop an analytical model and numerical analysis of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET, including the thickness, derived based on the formation of depletion depth to analyze the device performance at reducing dimensions.
Methods: The analysis is built upon the device's physical and electrical parameters, such as capacitance, electric field, thickness, threshold voltage, effective channel dimensions, drain current, are considered in this research. The depletion region in a MOSFET structure accounts for the inclusion of the source and drain depletion regions, divided primarily into three separate sub-regions as a junction between the diffused source/drain and the substrate depletion under the channel and by region induced by lateral source and drain diffusion. The condition of a planar MOSFET in channel formation, i.e., for strong inversion, and when VGS > VTH has been considered for this mathematical analysis.
Results: The computed results of device thickness and depending parameters for a planar MOSFET and the CSDG MOSFET have been obtained. Based on this analysis, the silicon thickness of the typical CSDG MOSFET computed is 180 nm, 281 nm, and 327 nm at VDS 0.2 V, 0.8 V, and 1.2 V, respectively. The achieved results, through the thickness modeling proposed in this work, show that nanoscale CSDG MOSFET can be deployed for the improvements in the device performance and novel design modifications.
Conclusion: The analysis presented in this work significantly contributes to understanding the dependence of semiconductor thickness in CSDG MOSFET and serves as a guide for future modifications in the structure for the device compactness.
Short channel MOSFET, junction depletion, thickness modeling, Cylindrical Surrounding Double-Gate (CSDG), microelectronics, nanotechnology, VLSI.
Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban-4041, Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban-4041