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A New Keeper Domino Logic Based Full Adder for High-Speed Arithmetic Circuits

Author(s):

Deepika Bansal*, Bal Chand Nagar, Ajay Kumar and Brahamdeo Prasad Singh   Pages 1 - 10 ( 10 )

Abstract:


Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET.

Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature.

Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies.

Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

Keywords:

Carbon nanotube MOSFET, Dynamic Logic, Keeper circuits, Silicon MOSFET, stack effect, transistor.

Affiliation:

Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan, Department of Electronics and Communication Engineering, National Institute of Technology Patna, Department of Electronics and Communication Engineering, Manipal University Jaipur, Rajasthan, Department of Electronics and Communication Engineering, Netaji Subhas Institute of Technology Delhi



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