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A Survey on Low Power Design Approaches in Nanoscale Regime

Author(s):

Vijay Kumar Sharma*   Pages 1 - 17 ( 17 )

Abstract:


Background: The increased demand of battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality and faster response at lower technology nodes. The applied power supply and threshold voltage of the individual device is scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current.

Objective: Leakage current should be made recessive with the continuous scaling of technology nodes.

Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design.

Results: 3-input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques.

Conclusion: INDEP approach is the most effective approach to reduce the leakage current and improving the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.

Keywords:

Device scaling, nanoscale CMOS, leakage power, VLSI circuits, stacking, MTCMOS, sleepy stack, sleepy keeper, DTCMOS, DTMOS, VTCMOS, SCCMOS, zigzag approach, LECTOR, GALEOR, VCLEARIT, control point insertion, bootstrapped approach, ONOFIC, INDEP

Affiliation:

School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University, Katra - 182320



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