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Design of Reversible Shift Register Using Reduced Number of Logic Gates

[ Vol. 12 , Issue. 1 ]

Author(s):

Heranmoy Maity*, Sudipta Banerjee, Arindam Biswas, Anita Pal and Anup Kumar Bhattacharjee   Pages 33 - 37 ( 5 )

Abstract:


Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial- in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

Keywords:

Reversible logic gate, flip-flop, delay, shift register, garbage output, VLSI.

Affiliation:

NSHM Knowledge Campus Durgapur, West Bengal, NSHM Knowledge Campus Durgapur, West Bengal, Kazi Nazrul University, West Bengal, National Institute of Technology Durgapur, West Bengal, National Institute of Technology Durgapur, West Bengal



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